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TLE 6244X 18 Channel Smart Lowside Switch
ASSP for Powertrain
Final Data Sheet
Features
* * * * * * * * Short Circuit Protection Overtemperature Protection Overvoltage Protection 16 bit Serial Data Input and Diagnostic Output (2 bit/chan. acc. SPI Protocol) Direct Parallel Control of 16 channels for PWM Applications Low Quiescent Current Compatible with 3.3V Microcontrollers Electrostatic discharge (ESD) Protection
P-MQFM 64-10
Ordering Code: Q67007-A9613
General description 18-fold Low-Side Switch (0.35 to 1 ) in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and 18 open drain DMOS output stages. The TLE6244X is protected by embedded protection functions and designed for automotive and industrial applications. The output stages are controlled via SPI Interface. Additionally 16 of the 18 channels can be controlled direct in parallel for PWM applications. Therefore the TLE6244X is particularly suitable for engine management and powertrain systems.
VS
IN1 IN2
as Ch. 1 as Ch. 1 as Ch. 1 as Ch. 1 as Ch. 1
V BB
LOGIC
Protection Functions
Output Stage
16
OUT1
IN15 IN16 SCLK SI
as Ch. 1 as Ch. 1
1
16
Serial Interface SPI
Output Control Buffer
OUT18
SO GND
Final Data Sheet
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1. Description
1.1 Short Description This circuit is available in MQFP64 package or as chip. 1.1.1 Features of the Power Stages Nominal Current Ron,max at TJ = 25C OUT1, 2, 5, 6 OUT3, OUT4 OUT7, OUT8 OUT9, OUT10 OUT11...OUT14 OUT15, OUT16 OUT17, OUT18 *) 2.2A 2.2A 1.1A 2.2A 2.2A 3.0A 1.1A 400m 380m 780m 380m 380m 280m 780m static current limitation enabled by SPI X X X Clamping 70V 70V 45V 45V 45V 45V 45V
*) only serial control possible (via SPI) Parallel connection of power stages is possible (see 1.13) Internal short-circuit protection Phase relation: non-inverting (exception: IN8->OUT8 is inverting) 1.1.2 Diagnostic Features The following types of error can be detected: Short-circuit to UBatt (SCB) Short-circuit to ground (SCG) Open load (OL) Overtemperature (OT) Individual detection for each output. Serial transmission of the error code via SPI. 1.1.3 VDD-Monitoring Low signal at pin ABE and shut-off of the power stages if VDD is out of the permitted range. Exception: If OUT8 is controlled by IN8, OUT8 will only be switched off by the overvoltage detection and not by undervoltage detection. The state of VDD can be read out via SPI. 1.1.4 sec-bus Alternatively to the parallel and SPI control of the power stages, a high speed serial bus interface can be configured as control of the power stages OUT1...OUT7 and OUT9...OUT16. 1.1.5 Power Stage OUT8 OUT8 can be controlled by SPI or by the pin IN8 only. When controlled by IN8 this power stage is functional if the voltage at the pin VDD is above 3,5V. OUT8 will not be reset by RST. In SPI mode the power stage is fully supervised by the VDD-monitor.
Final Data Sheet
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1.2 Block Diagram
UBatt
fault
diagnostics
OUT1
IN1 2,2A / 70V SPI IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 IN16 2,2A / 70V 2,2A / 70V 2,2A / 70V 2,2A / 70V 2,2A / 70V 1.1A / 45V 1.1A / 45V 2,2A / 45V 2,2A / 45V 2,2A / 45V 2,2A / 45V 2,2A / 45V 2,2A / 45V 3,0A / 45V 3,0A / 45V OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18
control only via SPI possible control only via SPI possible IN6 IN7 IN16 sec - Bus
SCK SI SS
1.1A / 45V 1.1A / 45V
VDD
SPI Interface
VDD-Monitoring
GND1...8 GND_ABE
VDD ABE
SO
RST
Final Data Sheet
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1.3 Description of the Power Stages
OUT1... OUT6
6 non-inverting low side power switches for nominal currents up to 2.2A. Control is possible by input pins, by the sec-bus or via SPI. For TJ = 25C the on-resistance of the power switches is below 400m. An integrated zener diode limits the output voltage to 70V typically. A protection for inverse current is implemented for OUT1... OUT4 for use as stepper-motor control.
OUT9... OUT14
6 non-inverting low side power switches for nominal currents up to 2.2A. Control is possible by input pins, by the sec-bus or via SPI. For TJ = 25C the on-resistance of the power switches is below 380m. An integrated zener diode limits the output voltage to 45V typically.
OUT15, OUT16
2 non-inverting low side power switches for nominal currents up to 3.0A. Control is possible by input pins, by the sec-bus or via SPI. For TJ = 25C the on-resistance of the power switches is below 280m. An integrated zener diode limits the output voltage to 45V typically.
OUT7, OUT8, OUT17, OUT18
4 low side power switches for nominal currents up to 1100mA. Stage 7 is non-inverting, Stage 8 is inverting (IN8 = `1' => OUT8 is active). For the output OUT7 control is possible by the input pin, by the sec-bus or via SPI, OUT8 is controlled by the input pin IN8 or via SPI, for the outputs OUT17 and OUT18 control is only possible via SPI. For TJ = 25C the on-resistance of the power switches is below 780m. An integrated zener diode limits the output voltage to 45V typically. In order to increase the switching current or to reduce the power dissipation parallel connection of power stages is possible (for additional information see 1.13). The power stages are short-circuit proof: Power stages OUT1...OUT8, OUT11.14: In case of overload (SCB) they will be turned off after a given delay time. During this delay time the output current is limited by an internal current control loop. Power stages OUT9, OUT10, OUT15...OUT18: In case of SCB these power stages can be configured for a shut-down mode or for static current limitation. In the shut down mode while SCB they will behave like OUT1..8 or OUT11..14. In case of static current limitation and SCB the current is limited and the corresponding bit combination is set (early warning) after a given delay time. They will not be turned off. If this condition leads to an overtemperature condition, the output will be set into a low duty cycle PWM (selective thermal shut- down with restart) to prevent critical chip temperature. There are 3 possibilities to turn the power stages on again: - turn the power stage off and on, either via serial control (SPI) or via parallel control (input pin, except outputs OUT17 and OUT18) or by the sec-bus (except OUT8, OUT17,OUT18) - applying a reset signal. - sending the instruction "del_dia" by the SPI-interface The VDD-monitoring locks all power stages, except OUT8 for access by the IN8 input. OUT8 is locked by an internal threshold of 3,5V maximum when controlled by IN8. Otherwise OUT8 is locked by the VDD-monitor.
Final Data Sheet
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All low side switches are equipped with fault diagnostic functions: - short-circuit to UBatt: - short-circuit to ground: - open load: - overtemperature: (SCB) can be detected if switches are turned on (SCG) can be detected if switches are turned off (OL) can be detected if switches are turned off (OT) will only be detected if switches are turned on
The fault conditions SCB, SCG, OL and OT will not be stored until an integrated filtering time is expired (please note for PWM application). If, at one output, several errors occur in a sequence, always the last detected error will be stored (with filtering time). All fault conditions are encoded in two bits per switch and are stored in the corresponding SPI registers. Additionally there are two central diagnostic bits: one specially for OT and one for fault occurrence at any output. The registers can be read out via SPI. After each read out cycle the registers have to be cleared by the DEL_DIA command. 1.3.1 Power Stage OUT8 (Condensed Description) 1.3.1.1 Control of OUT8 and VDD-Monitoring OUT8 can be controlled by SPI or by the pin IN8 only, control by s-bus is not possible. When controlled by IN8 this power stage is functional if the voltage at the pin VDD is above 3,5V. In SPI mode the power stage is fully supervised by the VDD-monitor. If OUT8 is controlled by IN8, OUT8 will only be switched off by the overvoltage detection and not by undervoltage detection. 1.3.1.2 Phase Relation IN8 - OUT8 The phase relation IN8 -> OUT8 is inverting. OUT8 is active if IN8 is set to logic '1' (high level, see 3.4.2 ) in case of parallel access. On executing the read instruction on RD_INP1/2 the inverted status of IN8 is read back. 1.3.1.3 Reset / Power Stage Diagnostics If OUT8 is controlled by IN8, OUT8 will not be reseted by RST. After reset parallel control (by IN8) is active for OUT8. If UVDD < 4.5V errors are not stored because of the active RST of the external Regulator. Nevertheless OUT8 is protected against overload. 1.3.1.4 Input Current The control input IN8 has an internal pull-down current source. Thus the input currents I IN8 are positive (flow into the pin). 1.3.1.5 On Resistance For OUT8 and 3.5V < UVDD < 4.5V R on increases (see 3.8.5). 1.3.1.6 Parallel Connection of Power Stages Parallel connection of power stages with OUT8 and parallel control is prohibited (inverting input IN8). Control via SPI is possible. See 1.13.
Final Data Sheet
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1.4 Pinout Function Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 or FDA Input 7 or SSY Input 8 Input 9 Input 10 Input 11 Input 12 Input 13 Input 14 Input 15 Input 16 or FCL Pin IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 IN16 Pin Number 7 46 10 43 6 63 61 22 20 33 5 48 13 40 1 62
Output 1 OUT1 8 Output 2 OUT2 45 Output 3 OUT3 9 Output 4 OUT4 44 Output 5_1 OUT5_1 16 Output 5_2 OUT5_2 17 Output 6_1 OUT6_1 37 Output 6_2 OUT6_2 36 Output 7 OUT7 60 Output 8 OUT8 57 Output 9_1 OUT9_1 18 Output 9_2 OUT9_2 19 Output 10_1 OUT10_1 35 Output 10_2 OUT10_2 34 Output 11 OUT11 4 Output 12 OUT12 49 Output 13_1 OUT13_1 14 Output 13_2 OUT13_2 15 Output 14_1 OUT14_1 39 Output 14_2 OUT14_2 38 Output 15_1 OUT15_1 2 Output 15_2 OUT15_2 3 Output 16_1 OUT16_1 51 Output 16_2 OUT16_2 50 Output 17 OUT17 25 Output 18 OUT18 28 (Note: OUTxy_1 and OUTxy_2 have to be connected externally!) Slave Select Serial Output Serial Input SPI Clock SS SO SI SCK 56 53 55 54
Final Data Sheet
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Supply Voltage VDD Supply Voltage UBatt GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 Sense Ground VDD-Monitoring In-/Output VDD-Monitoring Reset (low active) not connected
VDD Ubatt GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND_ABE ABE RST nc
47 23 26 27 58 59 11 12 42 41 29 30 31 21, 24, 32, 52, 64
64 nc
63 IN6 / FDA
62 IN16 / FCL
61 IN7 / SSY
60 OUT7
59 GND4
58 GND3
57 OUT8
56 SS
55 SI
54 SCK
53 SO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
IN15 OUT15_1 OUT15_2 OUT11 IN11 IN5 IN1 OUT1 OUT3 IN3 GND5 GND6 IN13 OUT13_1 OUT13_2 OUT5_1 OUT5_2 OUT9_1 OUT9_2 IN9 GND_ABE
nc 52 OUT16_1 51 OUT16_2 50 OUT12 49 IN12 48 VDD 47 IN2 46 OUT2 45 OUT4 44
HiQUAD64
IN4 43 GND7 42 GND8 41 IN14 40 OUT14_1 39 OUT14_2 38 OUT6_1 37 OUT6_2 36 OUT10_1 35 OUT10_2 34 IN10 33
OUT18
OUT17
GND2
GND1
Ubatt
ABE
RST
IN8 22
n.c.
nc
nc 21
23
24
25
26
27
28
29
30
31
32
Final Data Sheet
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1.5 Function of Pins IN1 to IN16 Control inputs of the power stages Internal pull-up current sources (exception: IN8 with pull-down current source) FCL FDA SSY OUT1 to OUT18 Clock for the sec-bus (pin shared with IN16) Data for the sec-bus (pin shared with IN6) Strobe and Synchronisation for the sec-bus (pin shared with IN7) Outputs of the power switches Short-circuit proof Low side switches Limitation of the output voltage by zener diodes VDD UBatt Supply voltage 5V Supply voltage UBatt Pin must not be left open but has to be connected either to UBatt or to VDD (e.g. in commercial vehicles) GND1 to GND8 Ground pins Ground pins for the power stages (see 2.4) Ground reference of all logic signals is GND1/2 RST Reset Active low Locks all power switches regardless of their input signals (except OUT8) Clears the fault registers Resets the sec-bus interface registers ABE In-/Output VDD-Monitoring Active low Output pin for the VDD-Monitoring Input pin for the shut-off signal coming from the supervisor GND_ABE SI, SO, SCK, SS Sense ground VDD-Monitoring SPI Interface
Final Data Sheet
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1.6 SPI Interface The serial SPI interface establishes a communication link between TLE6244X and the systems microcontroller. TLE6244X always operates in slave mode whereas the controller provides the master function. The maximum baud rate is 5 MBaud. The TLE6244X is selected by the SPI master by an active slave select signal at SS and by the first two bits of the SPI instruction.SI is the data input (Slave In), SO the data output (Slave Out). Via SCK (Serial Clock Input) the SPI clock is provided by the master. In case of inactive slave select signal (High) the data output SO goes into tristate. Block Diagram:
Power Stages 1..18
Power Stages 1..16
SCON_REG1...3
MUX_REG1,2
SS SCK SI SO Shift Register
SPI Control:
State Machine Clock Counter Control Bits Parity Generator
STATCON_REG
DIA_REG1...5
VDD-Monitoring
Power Stages 1..18
Final Data Sheet
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A SPI communication always starts with a SPI instruction sent from the controller to TLE6244X. During a write cycle the controller sends the data after the SPI instruction, beginning with the MSB. During a reading cycle, after having received the SPI instruction, TLE6244X sends the corresponding data to the controller, also starting with the MSB. SPI Command/Format: MSB
7 0 6 0 5 INSTR4 4 INSTR3 3 INSTR2 2 INSTR1 1 INSTR0 0 INSW
Bit 7,6 5-1 0
Name CPAD1,0 INSTR (4-0) INSW
Description Chip Address (has to be `0', `0') SPI instruction (encoding) Parity of the instruction
Characteristics of the SPI Interface: 1) If the slave select signal at SS is High, the SPI-logic is set on default condition, i.e. it expects an instruction. 2) If the 5V-reset (RST) is active, the SPI output SO is switched into tristate. The VDD monitoring (ABE) has no influence on the SPI interface. 3) Verification byte: Simultaneously to the receipt of an SPI instruction TLE6244X transmits a verification byte via the output SO to the controller. This byte indicates regular or irregular operation of the SPI. It contains an initial bit pattern and a flag indicating an invalid instruction of the previous access. 4) On a read access the databits at the SPI input SI are rejected. On a writing access or after the DEL_DIA instruction the TLE6244XTLE6244X sets the SPI output SO to low after sending the verification byte. If more than 16 bits are received the rest of the frame is rejected. 5) Invalid instruction/access: An instruction is invalid, if one of the following conditions is fulfilled: - an unused instruction code is detected (see tables with SPI instructions) - in case the previous transmission is not completed in terms of internal data processing - number of SPI clock pulses counted during active SS differs from exactly 16 clock pulses. A write access and the instruction DEL_DIA is internally suppressed (i.e internal registers will not be affected) in all cases where at the rising (inactive) edge of SS the number of falling edges applied to the SPI input SCK during the access is not equal to 16. A write access is also internally suppressed (i.e internal registers will not be affected) if at the rising (inactive) edge of SS a 17th bit is submitted (SCK=`1'). After the bits CPAD1,0 and INSTR (4-0) have been sent from the microcontroller TLE6244X is able to check if the instruction code is valid. If an invalid instruction is detected, any modification on a register of TLE6244X is not allowed and the data byte `FFh' is transmitted after having sent the verification byte. If a valid read instruction is detected the content of the corresponding register is transmitted to the controller after having sent the verification byte (even if bit INSW afterwards is wrong). If a valid write instruction is
Final Data Sheet
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detected the data byte '00h' is transmitted to the controller after having sent the verification byte (even if bit INSW afterwards is wrong) but modifications on any register of TLE6244 are not allowed until bit INSW is valid, too. If an invalid instruction is detected bit TRANS_F in the following verification byte is set to 'High'. This bit must not be cleared before it has been sent to the microcontroller. 6) If TLE6244X and additional IC's are connected to one common slave select, they are distinguished by the chip address (CPAD1, CPAD0). If an IC with 32bit-transmission-format is selected, TLE6232 must not be activated, even if slave select is set to 'low' and the first two bits of the third byte of the 32bit-transmission are identical to the chip address of TLE6244X. During the transmission of CPAD1 and CPAD0 the data output SO remains in tristate (see timing diagram of the SPI in chapter 3.9. ). SPI access format:
WRITE-access (16bit) 8 bit command + 8bit data SS SS
READ-access (16bit) 8 bit command + 8bit data
SI
SPI instruction MSB Check byte ZZ + 6bit MSB
Data 8bit
SI
SPI instruction MSB
XX XX XX XX
SO
00 00 00 00
SO Z=tristate
Check byte ZZ + 6bit
Data 8bit MSB
Verification byte: MSB
7 Z 6 Z 5 1 4 0 3 1 2 0 1 1 0 TRANS_F
Bit 0
Name TRANS_F
Description Bit = 1: error detected during previous transfer Bit = 0: previous transfer was recognised as valid State after reset: 0 Fixed to High Fixed to Low Fixed to High Fixed to Low Fixed to High send as high impedance send as high impedance
1 2 3 4 5 6 7
Final Data Sheet
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SPI Instructions
SPI Instruction
Encoding
bit 7,6 bit 5,4,3,2,1 CPAD1,0 INSTR(4...0) Parity
Description
RD_IDENT1 RD_IDENT2 WR_STATCON WR_MUX1 WR_MUX2 WR_SCON1 WR_SCON2 WR_SCON3 WR_CONFIG RD_MUX1 RD_MUX2 RD_SCON1 RD_SCON2 RD_SCON3 RD_STATCON DEL_DIA RD_DIA1 RD_DIA2 RD_DIA3 RD_DIA4 RD_DIA5 RD_CONFIG RD_INP1 RD_INP2
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000 00001 10001 10010 10011 10100 10101 10110 10111 00010 00011 00100 00101 00110 00111 11000 01000 01001 01010 01011 01100 01101 01110 01111 all others
0 1 0 0 1 0 1 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 1 0
read identifier 1 read identifier2 write into STATCON_REG write into MUX_REG1 write into MUX_REG2 write into SCON_REG1 write into SCON_REG2 write into SCON_REG3 write into CONFIG read MUX_REG1 read MUX_REG2 read SCON_REG1 read SCON_REG2 read SCON_REG3 read STATCON_REG resets the 5 diagnostic registers DIA_REG read DIA_REG1 read DIA_REG2 read DIA_REG3 read DIA_REG4 read DIA_REG5 read CONFIG read INP_REG1 read INP_REG2 no function
Final Data Sheet
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1.6.1 Serial/Parallel Control Serial/Parallel Control of the Power Stages 1...16 and Serial Control (SPI) of the Power Stages 17 and 18: The registers MUX_REG1/2 and the bmux-bit prescribe parallel control or serial control (SPI or secbus) of the power stages. (SPI-Instructions: WR_MUX1...2, RD_MUX1...2, WR_SCON1...3, RD_SCON1...3) The following table shows the truth table for the control of the power stages 1...18. The registers MUX_REG1, 2 prescribe parallel-control or serial control of the power stages. The registers SCON_REG1...3 prescribe the state of the power stage in case of SPI-serial control. BMUX determines parallel control or control by sec-bus. For the power stages 17 and 18 control is exclusively possible via SCON17/18. IN17/18 and MUX17/18 do not exist. BMUX has no function for OUT17/18. ABE 0 0 1 1 1 1 1 1 1 RST 0 1 0 1 1 1 1 1 1 INx X X X X X 0 1 X X BMUX X X X X X 1 1 0 0 MUXx SCONx X X X 0 0 1 1 1 1 X X X 0 1 X X X X secREGx X X X X X X X 0 1 Output OUTx of Power Stage x, x = 1..18 OUTx off OUTx off OUTx off SPI Control: OUTx on SPI Control: OUTx off Parallel Control: OUTx on Parallel Control: OUTx off sec-bus Control: OUTx on sec-bus Control: OUTx off
Exception: OUT8 is on (active) if IN8 is set to logic `1' (and off if IN8 is set to logic `0') in case of parallel access. Note: OUT8 cannot be controlled by the sec-Bus. Refer to section 1.7.
Final Data Sheet
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Description of the SPI Registers Register:
7 MUX7
MUX_REG1
6 MUX6 5 MUX5 4 MUX4 3 MUX3 2 MUX2 1 MUX1 0 MUX0
State of Reset: 80H Access by Controller: Bit 0 1 2 3 4 5 6 7 Name MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 Read/Write Description Serial or parallel control of power stage 1 Serial or parallel control of power stage 2 Serial or parallel control of power stage 3 Serial or parallel control of power stage 4 Serial or parallel control of power stage 5 Serial or parallel control of power stage 6 Serial or parallel control of power stage 7 Serial or parallel control of power stage 8
Register:
7 MUX15
MUX_REG2
6 MUX14 5 MUX13 4 MUX12 3 MUX11 2 MUX10 1 MUX9 0 MUX8
State of Reset: 00H Access by Controller: Bit 0 1 2 3 4 5 6 7 Name MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX14 MUX15 Read/Write Description Serial or parallel control of power stage 9 Serial or parallel control of power stage 10 Serial or parallel control of power stage 11 Serial or parallel control of power stage 12 Serial or parallel control of power stage 13 Serial or parallel control of power stage 14 Serial or parallel control of power stage 15 Serial or parallel control of power stage 16
Final Data Sheet
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Register:
7 SCON7
SCON_REG1
6 SCON6 5 SCON5 4 SCON4 3 SCON3 2 SCON2 1 SCON1 0 SCON0
State of Reset: FFH Access by Controller: Bit 0 1 2 3 4 5 6 7 Name SCON0 SCON1 SCON2 SCON3 SCON4 SCON5 SCON6 SCON7 Read/Write Description State of serial control of power stage 1 State of serial control of power stage 2 State of serial control of power stage 3 State of serial control of power stage 4 State of serial control of power stage 5 State of serial control of power stage 6 State of serial control of power stage 7 State of serial control of power stage 8
Register:
7 SCON15
SCON_REG2
6 SCON14 5 SCON13 4 SCON12 3 SCON11 2 SCON10 1 SCON9 0 SCON8
State of Reset: FFH Access by Controller: Bit 0 1 2 3 4 5 6 7 Name SCON8 SCON9 SCON10 SCON11 SCON12 SCON13 SCON14 SCON15 Read/Write Description State of serial control of power stage 9 State of serial control of power stage 10 State of serial control of power stage 11 State of serial control of power stage 12 State of serial control of power stage 13 State of serial control of power stage 14 State of serial control of power stage 15 State of serial control of power stage 16
Final Data Sheet
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Register:
7 1
SCON_REG3
6 1 5 1 4 1 3 1 2 1 1 SCON17 0 SCON16
State of Reset: FFH Access by Controller: Bit 0 1 7-2 Name SCON16 SCON17 Read/Write Description State of serial control of power stage 17 State of serial control of power stage 18 No function: HIGH on reading
Final Data Sheet
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1.6.2 Diagnostics/Encoding of Failures Description of the SPI Registers (SPI Instructions: RD_DIA1...5)
Register:
7 DIA7
DIA_REG1
6 DIA6 5 DIA5 4 DIA4 3 DIA3 2 DIA2 1 DIA1 0 DIA0
State of Reset: FFH Access by Controller: Bit 1-0 3-2 5-4 7-6 Name DIA (1-0) DIA (3-2) DIA (5-4) DIA (7-6) Read only Description Diagnostic Bits of power stage 1 Diagnostic Bits of power stage 2 Diagnostic Bits of power stage 3 Diagnostic Bits of power stage 4
Register:
7 DIA15
DIA_REG2
6 DIA14 5 DIA13 4 DIA12 3 DIA11 2 DIA10 1 DIA9 0 DIA8
State of Reset: FFH Access by Controller: Bit 1-0 3-2 5-4 7-6 Name DIA (9-8) DIA (11-10) DIA (13-12) DIA (15-14) Read only Description Diagnostic Bits of power stage 5 Diagnostic Bits of power stage 6 Diagnostic Bits of power stage 7 Diagnostic Bits of power stage 8
Final Data Sheet
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Register:
7 DIA23
DIA_REG3
6 DIA22 5 DIA21 4 DIA20 3 DIA19 2 DIA18 1 DIA17 0 DIA16
State of Reset: FFH Access by Controller: Bit 1-0 3-2 5-4 7-6 Name DIA (17-16) DIA (19-18) DIA (21-20) DIA (23-22) Read only Description Diagnostic Bits of power stage 9 Diagnostic Bits of power stage 10 Diagnostic Bits of power stage 11 Diagnostic Bits of power stage 12
Register:
7 DIA31
DIA_REG4
6 DIA30 5 DIA29 4 DIA28 3 DIA27 2 DIA26 1 DIA25 0 DIA24
State of Reset: FFH Access by Controller: Bit 1-0 3-2 5-4 7-6 Name DIA (25-24) DIA (27-26) DIA (29-28) DIA (31-30) Read only Description Diagnostic Bits of power stage 13 Diagnostic Bits of power stage 14 Diagnostic Bits of power stage 15 Diagnostic Bits of power stage 16
Final Data Sheet
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Register:
7 1
DIA_REG5
6 1 5 1 4 UBatt 3 DIA35 2 DIA34 1 DIA33 0 DIA32
State of Reset: FFH Access by Controller: Bit 1-0 3-2 4 Name DIA (33-32) DIA (35-34) UBatt Read only Description Diagnostic Bits of power stage 17 Diagnostic Bits of power stage 18 0: Voltage Level at Pin UBatt is below 2V (typically) 1: Voltage Level at Pin UBatt is above 2V (typically) Diagnosis of UBatt is only possible if UVDD > 4.5V Status of UBatt is not latched. No function: High on reading
7-5
Encoding of the Diagnostic Bits of the Power Stages DIA(2*x-1) 1 1 0 0 DIA(2*x-2) 1 0 1 0 State of power stage x Power stage o.k. Short-circuit to UBatt (SCB) / OT Open load (OL) Short-circuit to ground (SCG) x = 1..18
Final Data Sheet
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1.6.3 Configuration The sec-bus is enabled by this register. In addition the shut off at SCB can be configured for the power-stages OUT9, OUT10 and OUT15... OUT18.
CONFIG (Read and write)
7 O16-SCB 6 O15-SCB 5 O10-SCB 4 O9-SCB 3 O18-SCB 2 O17-SCB 1 BMUX 0 1
State of Reset: FFh Bit 0 1 2 3 4 5 6 7 BMUX O17-SCB O18-SCB O9-SCB O10-SCB O15-SCB O16-SCB Name Description No function: HIGH on reading 1: parallel inputs INx enabled 0: sec-Bus Interface enabled 1: The output OUT17 is switched off in case of SCB 0: The output is not switched off in case of SCB 1: The output OUT18 is switched off in case of SCB 0: The output is not switched off in case of SCB 1: The output OUT9 is switched off in case of SCB 0: The output is not switched off in case of SCB 1: The output OUT10 is switched off in case of SCB 0: The output is not switched off in case of SCB 1: The output OUT15 is switched off in case of SCB 0: The output is not switched off in case of SCB 1: The output OUT16 s switched off in case of SCB 0: The output is not switched off in case of SCB
Description of the sec-bus see chapter 1.7
Final Data Sheet
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TLE 6244X
1.6.4 Other Reading the IC Identifier (SPI Instruction: RD_IDENT1):
IC Identifier1 (Device ID)
7 ID7 6 ID6 5 ID5 4 ID4 3 ID3 2 ID2 1 ID1 0 ID0
Bit 7...0
Name ID(7...0)
Description ID-No.: 10101000
Reading the IC revision number (SPI Instruction: RD_IDENT2):
IC revision number
7 SWR3 6 SWR2 5 SWR1 4 SWR0 3 MSR3 2 MSR2 1 MSR1 0 MSR0
Bit 7...4 3...0
Name SWR(3...0) MSR(3...0)
Description Revision corresponding to Software release: 0Hex Revision corresponding to Maskset: 0Hex
Reset of the Diagnostic Information (SPI Instruction: DEL_DIA): Resets the 5 diagnostic registers DIA_REG1...5 to FFH and the common overtemperature flag in register STATCON_REG (Bit4) to High. These bits are only cleared by the DEL_DIA instruction when there is no failure entry at the input of the registers. Access is performed like a writing access with any data byte. In the case a power stage is shut off because of SCB, the output is activated again by the DEL_DIA instruction and the filtering-time is enabled. Therefore in case of SCB the output is activated and shut off after the shutoff delay. For a power stage in the current limitation mode, the current limitation mode is left, if a DEL_DIA instruction has been received. If there is still the condition for SCB the current limitation mode is entered again. On the following pages the conditions for set and reset of the SCB report in DIA_REGx is shown in several schematics. The signal power stage control" is generated as follows: INi="ON" SPI="ON" sec="ON" OR ABE not active AND
power stage control = ON"
Final Data Sheet
21
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Final Data Sheet
Schematic of SCB report of power stages OUT1...7,9...18 (power stage programmed for shut-off in case of SCB), SCB entry deleted by DEL_DIA after SCB condition disappeared and power stage control was toggled
SCB condition SCB tDIAG On On On tDIAG
no SCB
tDIAG
tDIAG
OUTx
On
On
On
Fault entry in DIA_REGx
SCB
SCB
SCB
22
DEL_DIA command
Reset
power stage control On
On
On
On
On
TLE 6244X
V4.2, 2003-08-29
Final Data Sheet
Schematic of SCB report of power stages OUT1...7,9...18 (power stage programmed for shut-off in case of SCB), SCB entry deleted by Reset after SCB condition disappeared and power stage control was toggled
SCB tDIAG tDIAG On On On On no SCB
SCB condition
tDIAG
tDIAG
OUTx
On
On
Fault entry in DIA_REGx
SCB
SCB
SCB
23
DEL_DIA command
Reset
power stage control On
TLE 6244X
V4.2, 2003-08-29
On
On
On
On
Final Data Sheet
Schematic of SCB report of power stages OUT1...7,9...18 (power stage programmed for shut-off in case of SCB), SCB entry deleted by DEL_DIA after SCB condition disappeared but power stage control was not toggled
SCB tDIAG tDIAG On On On On no SCB
SCB condition
tDIAG
tDIAG
OUTx
On
On
Fault entry in DIA_REGx
SCB
SCB
SCB
24
DEL_DIA command
Reset
power stage control On
TLE 6244X
V4.2, 2003-08-29
On
On
On
Final Data Sheet
Schematic of SCB report of power stages OUT1...7,9...18 (power stage programmed for shut-off in case of SCB), SCB entry deleted by Reset after SCB condition disappeared but power stage control was not toggled
SCB tDIAG On On On tDIAG no SCB
SCB condition
tDIAG
tDIAG
OUTx
On
On
Fault entry in DIA_REGx
SCB
SCB
SCB
25
DEL_DIA command
Reset
power stage control On
TLE 6244X
V4.2, 2003-08-29
On
On
On
Final Data Sheet
Schematic of SCB report of power stages OUT9,10,15...18 (power stage programmed for current limitation in case of SCB), SCB resp. OT flag entry deleted exemplary by DEL_DIA after SCB resp. OT condition disappeared and power stage control was toggled
SCB no SCB OT tDIA,OT tDIA,OT On tDIAG
SCB
SCB condition no OT no OT
OT condition
OUTx On
On
On
On
tDIAG SCB OT
tDIAG
26
Fault entry in DIA_REGx
SCB
common OT flag in STATCON_REG
DEL_DIA command
Reset On On On
TLE 6244X
V4.2, 2003-08-29
power stage control
On
TLE 6244X
Reading Input1 (SPI Instruction: RD_INP1) : Register INP_REG1
7 IN8 6 Test 5 0 4 IN5 3 IN4 2 IN3 1 IN2 0 IN1
Bit 0..4 5 6 7
Name IN(1...5) Test IN8
Description Status of the input pins IN1... IN5 No function: LOW on reading sec-test-bit, the bit D8 of the sec-bus is read Inverted status of the input pin IN8: Low level at pin IN8: Bit 7 = 1 High level at pin IN8: Bit 7 = 0
Reading Input2 (SPI Instruction: RD_INP2):
Register INP_REG2
7 0 6 IN15 5 IN14 4 IN13 3 IN12 2 IN11 1 IN10 0 IN9
Bit 0..6 7
Name IN9...IN15
Description Status of the input pins IN9...IN15 No function: LOW on reading
The input pins IN1..IN5 and IN8...IN15 can be used as input port expander by reading the status of the input pins using the SPI-commands RD_INP1/2. If the sec-bus-interface is enabled (BMUX=0) the pull-up current sources at the input IN1..5 and IN9..15 are disabled. If BMUX=1 the pullup current sources at these pins are enabled. The pull-up/pull-down current sources of the other input pins are not effected by the bit BMUX. On executing the read instruction on RD_INP1/2, the present status (not latched) of the input pins INx is read back (exception: bit IN8 represents the inverted status of input pin IN8).
Final Data Sheet
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TLE 6244X
Reading the State resp. the Configuration: (SPI Instructions: WR_STATCON, RD_STATCON) Register:
7 CONFIG2
STATCON_REG
6 CONFIG1 5 CONFIG0 4 STATUS4 3 STATUS3 2 STATUS2 1 STATUS1 0 STATUS0
Bit 0
Name STATUS0
Description Bit = 1: No overvoltage at VDD Bit = 0: Overvoltage at VDD resp. state of overvoltage still stored (reset by CONFIG0 = 0) Access by Controller: Read only
Overvoltage information (bit STATUS0 = 0) will not be reset by an external reset signal (pin RST=low). Overvoltage will be detected and stored (CONFIG0 = 1) during RST=low. The information will be deleted when an internal (undervoltage) reset occurs or when CONFIG0 is set to 0.
1
STATUS1
Bit = 1: No undervoltage at VDD Bit = 0: Undervoltage at VDD Access by Controller: Read only Reading the voltage level at ABE Access by Controller: Read only Common error flag Bit =1: At present no error is entered in one of the 5 diagnostic registers DIA_REG1..5. Bit = 0: For at least at one power stage an error has been detected and entered in the corresponding diagnostic register. Access by Controller: Read only Common overtemperature flag Bit = 1: No overtemperature detected since the last reset of diagnostic information (by del_dia instruction, RST = Low or undervoltage at VDD (see 3.2. )) Bit = 0: Overtemperature for at least one power stage has been detected since the last reset of the diagnostic information (by del_dia instruction, RST = Low or undervoltage at VDD (see 3.2. )) State of Reset: 1 Access by Controller: Read only Bit = 1: Latch function for overvoltage at VDD is switched on Bit = 0: Latch function for overvoltage at VDD is switched off State of Reset: 1 Access by Controller: Read/Write
2 3
STATUS2 STATUS3
4
STATUS4
5
CONFIG0
Final Data Sheet
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TLE 6244X
6
CONFIG1
Bit = 1: Lower threshold of VDD-monitoring is lifted if bit CONFIG2 = 0 (test of switch-off path) Bit = 0: Upper threshold of VDD-monitoring is reduced if bit CONFIG2 = 0 (test of switch-off path) State of Reset: 1 Access by Controller: Read/Write Bit = 1: Test of VDD threshold is switched off Bit = 0: Test of VDD threshold is switched on State of Reset: 1 Access by Controller: Read/Write
7
CONFIG2
Final Data Sheet
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TLE 6244X
1.7 sec - Bus Interface The sec-bus-interface is one of three possibilities to control the power stages. OUT1...OUT7 and OUT9...OUT16 are influenced by the reset input RST. If RST is set to Low, these power stages are switched off. After reset they are controlled by the SPI (default initialization of TLE6244X). Power stage 8 however is not influenced by the reset input if it's controlled by IN8 and UVDD > 3,5V. Alternatively these outputs can be controlled either by the pins IN1...IN16 or by the sec-bus interface. Exception: OUT8 can be controlled by IN8 or by the SPI-interface only. The bit 'Bus-Multiplex' (BMUX) in the SPI register CONFIG prescribes parallel access (IN1...IN7, IN9...IN16) or sec-bus control (see figure below). Exception: If BMUX is set to `0' only the powerstages OUT1...OUT7 and OUT9...OUT16 are controlled by the sec-bus. Main features: - 16 data bits for each data-frame (at the pin FDA) - 16 clock-pulses for each data-frame (at the pin FCL) - clock frequency TLE6244: 0...16 MHz - one sync -input (pin SSY) to latch the input data stream - input level interface same as for IN6, IN7, IN16 - no error correction
Data-Frame
SSY FCL FDA D0 D1 D14 D15 don't care D0
INx FDA FCL 16 bit shift register
BMUX
OUTx Glitch Filter 16 bit sec-bus Reg.
SSY
SPI
SCON_REG SPI-shift-reg MUX_REG
Principle of the sec-bus interface
Final Data Sheet
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TLE 6244X
When the bit BMUX in CONFIG is set to Low, the power stages 1...7 and 9...16 are controlled by the sec-bus-interface on condition that registers MUX_REG1/2 are configured for serial access. The received sec-bus bit stream (D0... D15) is latched into a 16-bit register by the rising edge at SSY. Power stages 1...7 and 9...16 are switched according to bits D0...D7 and D9...D15: sec-bus control of power stage OUT14 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 sec-bus control of power stage sec-bus Test Bit OUT11 OUT10 OUT9 OUT12 OUT13 OUT16 OUT15
D0 D1 D2 D3 D4 D5 D6 D7
D8 D9 D10 D11 D12 D13 D14 D15
Bit Dx = 0: Bit Dx = 1: State of reset:
Power stage OUTx is switched on Power stage OUTx is switched off FFFFH
Because the power stage 8 is not controlled by the sec-bus-interface, the corresponding bit D8 can be used as test bit, that can be read back by the SPI-interface (see register RD_INP1). If the sec-bus-interface is used to control the power stages, the input pins IN1..IN5 and IN8...IN15 can be used as input port expander by reading the status of the input pins by the SPIcommands RD_INP1/2.
Final Data Sheet
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TLE 6244X
1.8 Unused Power Stages To avoid an open load" fault indication an unused power switch has to be connected to an external pull up resistor connected to UUB or has to be switched on by the input pin or via SPI or the sec-bus-interface.
UUBatt
Voltage regulator
Udrop UBatt UBR TLE6244X OUTi
RPull-up UUB Idiag
UthresOL
RPull-up,max = (UBRmin - Udrop,max - UthresOL,max) / Idiag,max UBRmin is the required minimum battery voltage for diagnostic function of the ECU. The drop voltage is composed of the drop voltage of the regulator and the drop voltage of the reverse protection circuit of the regulator resp. the forward voltage of a reverse protection diode. Attention: This equation also applies to power switches that are used as signal drivers (pull up resistor inside ECU or outside ECU): the permissible pull up resistance without a wrong diagnostic information is calculated by the same equation. On dimensioning the pull up resistance in combination with the diagnostic current, in applications as signal drivers attention must be paid especially to the required high level (also for low battery voltage).
Final Data Sheet
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TLE 6244X
1.9 Timing Diagram of the Power Outputs 1.9.1 Power Stages
UINi
UINiH UINiL t UOUTi UCLi 0.8UCLi*)
UBATT 0.8UBATT son
soff
0.2UCLi 0.2UBATT tdon tson tdoff tsoff t
If the output is controlled via SPI the timing starts with the positive slope at SS If the output is controlled by the sec-bus, the timing starts with the pos. slope of SSY *) With ohmic load, UCLi = UBatt
Final Data Sheet
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TLE 6244X
1.10 VDD-Monitoring Overview: The VDD-monitoring generates a low" signal at the bidirectional pin ABE if the 5V supply voltage at pin VDD is out of the permissible range of 4.5V...5.5V. On ABE = low the power stages of TLE6244X are switched off. Exception: OUT8 is not switched off in case of parallel control via IN8 by the VDD monitoring undervoltage threshold, but by a threshold of 3.5V at VDD. On shorting pin ABE to VDD or UBATT ( 36V), the power stages will be switched off in case of undervoltage or overvoltage at pin VDD in spite of ABE = high. The behavior of the ABE level on the return of VDD out of the undervoltage range into the correct range is not configurable. At the transition from undervoltage to normal voltage the signal at pin ABE goes high after a filtering time is expired. The behavior of the ABE level on the return of VDD out of the overvoltage range into the correct range is configurable in STATCON_REG, Bit5. At the transition from overvoltage to normal voltage the signal at pin ABE goes high either after a filtering time (OV not latched) or after a SPI writing instruction (OV latched, state after reset). On undervoltage condition the signal at pin ABE goes high after a filtering time is expired. On overvoltage condition pin ABE goes high either after a filtering time or after a SPI writing instruction. Before this SPI instruction is sent to TLE6244X appropriate tests can be carried out by the controller. If the voltage at pin VDD is below the lower limit or is resp. was above the upper limit, this can be read out by the SPI instruction RD_STATCON. VDD-monitoring has no influence on SCON_REGx, MUX_REGx, DIA_REGx, CONFIG and INP_REGx. If output stages are switched off by the internal over-/undervoltage detection or by externally applying a low signal at the ABE pin, no failure storage (DIAREG1...5) may occur. Description in Detail: Description of the Register: STATCON_REG Bit 7 1: Normal operation 0: Test of VDD threshold Access by controller: read/write State of reset: 1 1: Testing the lower threshold (if bit 7 = 0) 0: Testing the upper threshold (if bit 7 = 0) Access by controller: read/write State of reset: 1 1: ABE latched after overvoltage 0: ABE deactivated immediately after the disappearance of the overvoltage Access by controller: read/write State of reset: 1 Reading out the level at pin ABE Access by controller: read only 1: no undervoltage at pin VDD 0: undervoltage at pin VDD Access by controller: read only
Bit 6
Bit 5
Bit 2 Bit 1
Final Data Sheet
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TLE 6244X
Bit 0
1: no overvoltage at pin VDD 0: overvoltage at pin VDD resp. state of overvoltage still stored Access by controller: read only
Testing the VDD-Monitoring: Upper threshold: By writing 000xxxxxb in the register STATCON_REG the overvoltage threshold is reduced by 0.8V. In STATCON_REG Bit 0 has to be LOW then. After writing 110xxxxxb in the register STATCON_REG Bit 0 in STATCON_REG must be HIGH again. Lower threshold: By writing 010xxxxxb in the register STATCON_REG the overvoltage threshold is increased by 0.8V. In STATCON_REG Bit 1 has to be LOW then. After writing 110xxxxxb in the register STATCON_REG Bit 1 in STATCON_REG must be HIGH again.
Example of configuration: Requirement: After overvoltage ABE is to be LOW; After overvoltage a self-test is carried out by the ECU, afterwards ABE is deactivated. Register STATCON_REG is set to 111xxxxxb during driving cycle. When ABE becomes active, overvoltage can be detected by reading out STATCON_REG. After the ECU's self-test a reset condition is achieved by writing 110xxxxxb into the register STATCON_REG. This reset is only possible after disappearance of the overvoltage condition because the set input is dominant. The reset signal is withdrawn by writing 111xxxxxb.
Final Data Sheet
35
V4.2, 2003-08-29
<=
0
1 X
default
Test: Undervoltage Threshold
TLE 6244X
V4.2, 2003-08-29
0 0 1
<=
Final Data Sheet
VDD VDD
1 0
Glitch filter Set dominant L" = Undervoltage at VDD
Block Diagram: VDD-Monitoring
+ -
ABE
1 S R
Undervoltage Reset
+ Q
&
GND1,2
100k
0
L" = Overvoltage at VDD
GND_ABE GND_ABE
36
7 6 5 4 3 2 1 0 Test: Overvoltage Threshold
1
>1
>1 1
&
L" = Switch Off
STATCON_REG
Power Stages
TLE 6244X
1.11 Notes for the Application in Commercial Vehicles _ For electric systems with 24V battery voltage, that can even increase to > 37V in case of load dump, some peculiarities have to be observed! The static voltage at pin UBatt without destruction is limited to 37V, therefore this pin must either be connected to the 5V supply voltage VDD or else the voltage at pin UBatt has to be limited by adequate external circuitry. By connecting pin UBatt to VDD the values of Rds, on of the power switches will increase up to 20%. The power stages 7...18 are equipped with a 40V active clamping. Therefore this power stages must only drive loads with an accordingly high resistance that can be switched on in case of overvoltage (e.g. a maximum load dump voltage of 60V and a load resistor of 1k result in a power dissipation of 0.8W for each power stage. For all of the 12 power stages together there is a power dissipation of 9.6W for the typical duration of a load dump of 500ms.). The restrictions listed above are no longer relevant in case of a overvoltage-protected battery voltage"within the 24V electric system that limits the voltage to e.g. a maximum of 37V. The thresholds of the currents, on which the power stages are switched off in case of overload, are increased by approximately 25% if there is a voltage at pin UBatt higher than19V (reason: jump start requirements in 12V electric systems). Exception: OUT9 and OUT10 and OUT15... OUT18. See characteristics in chapters 3.5.3, 3.6.3, 3.7.3 and 3.8.3. The restrictions concerning overload of power stages (see 3.5.2, 3.6.2, 3.7.2 and 3.8.2) and permissible clamping energy (see 3.5.8, 3.6.8, 3.7.8 and 3.8.8) are relevant further on. 1.11.1 Notes for short circuit limitation The power stages are short circuit protected for the following conditions: The max. voltage at the output pins are limited to 36V and the TLE6244 is not operating in the booster mode. The power stages will be switched on/off with a max. frequency of 1 kHz. Only a 40 msec burst with the 1 kHz on/off-frequency is allowed, with a minimum burst repetition time of 1 sec. The maximum number of burst repetition cycles is 25. The number of driving cycles under these conditions is limited to 100 in lifetime. The temperature of the slug of the MQFP64 package must not exceed 130C. These limitations are valid for UBatt > 24 V. For Ubatt 24 V the number of driving cycles under these conditions is extended to 1000 in lifetime.
Final Data Sheet
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TLE 6244X
1.12 Notes for the Diagnostics - SCB entry in DIA_REGx see diagrams in chapter 1.6.4. - In case of overvoltage at pin VDD (VDD > 5,5V) the diagnostic information can be wrong. In that case, the diagnostic information has to be cleared with the DEL_DIA instruction. - The filtering time restarts when the output voltage passes the diagnostic threshold for short to ground (SCG). - Diagram of the typical diagnostic current: IOUTPUT 580 A
A
A
3.5V 0V -130 A 2.7V 5V
B A
Short to GND
14V UOUT
A
Open load o. k.
C
A: Diagnostic current (see 3.11.3) B: Bias Voltage Open Load (see3.11.2) C: Short to GND Threshold (see 3.11.1.2) D: Open load Threshold (see 3.11.1.1)
D
Final Data Sheet
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Final Data Sheet
Toggling INx HIGH -> LOW SCB
No Fault No Action
Exemplary for a power stage controlled by input pin INx. Diagram is accordingly valid for serial control via SPI or sec-bus. The SPI instruction DEL_DIA deletes all fault registers in any state. On active reset resp. active ABE (VDD is out of range) output OUTx is switched off. After reset the power stage is in state A (except OUT8).
OL SCG
No Action
OT
No Fault
A INx HIGH OUTx off SCG OL
Debouncing No SCG No
Toggling INx LOW -> HIGH B INx LOW SCB OT
Debouncing Debouncing Current Control
Toggling INx LOW -> HIGH OUTx on
Debouncing
SCG SCB
No SCB
OL OL
Fault Entry 00 CSG Fault Entry 10 SCB
for OUT9..10 OUT15...16 (if current limitation is configured) for OUT9..10 (no current limitation) OUT15...16 for OUT1..8, OUT11..14
Fault Entry 01 OL
Fault Entry 10 OT
State Diagram of the Power Stages Diagnostics
39
OL SCB OT C INx LOW OUTx off Toggling INx LOW -> HIGH A D
No Fault
SCG
Fault Entry 10 SCB
OL SCG
No Action
INx LOW OUTx on max current 3..5A
Fault Entry 10 SCB
OT
no OT OT Fault Entry 10 OT Debouncing
no OT INx LOW OT OUTx off Toggling INx LOW -> HIGH
At DEL_DIA: C -> B D -> B A no action
A
TLE 6244X
V4.2, 2003-08-29
TLE 6244X
1.13 Parallel Connection of Power Stages The power stages (PS) which are connected in parallel have to be switched on and off simultaneously. The corresponding SPI-Bits SCONx have to be in the same register (see page 15), when the PS are serial controlled via SPI. In case of overload the ground current and the power dissipation are increasing. The application has to take into account that all maximum ratings are observed (e.g. operating temperature TJ and total ground current IGND, see page 36, 37).
Max. number of parallel connections: 3
The following statements apply to PS within the same TLE6244X The max. short circuit shutdown threshold of the parallel connected PS is the summation of the corresponding max. values of the PS (ISC,OUTx + ISC,OUTy +....).
Max. Nominal Current 2 symmetrical PS (see note 1) 2 PS of the same type (see note 2) 3 PS of the same type (see note 2)
Max. Clamping Energy
On Resistance
0.5 x Ron,OUTx,y
0.9 x (Imax,OUTx + Imax,OUTy) 0.75 x (ECl,OUTx + ECl,OUTy)
0.85 x (Imax,OUTx + Imax,OUTy) 0.75 x (ECl,OUTx + ECl,OUTy) 0.5 x Ron,OUTx,y 0,8 x (Imax,OUTx + Imax,OUTy+ Imax,OUTz) 0,58 x (ECl,OUTx + ECl,OUTy + ECl,OUTz)
0.34 x Ron,OUTx,y,z
2 PS with the same nominal 0.7 x (Imax,OUTx + Imax,OUTy) Clamping energy current, but different clampof the PS with the lower ing voltage (application withclamping voltage out free-wheeling-diode) (see note 3) 2 PS with the same nominal 0.7 x (Imax,OUTx + Imax,OUTy) no clamping required current, but different clamping voltage (application with free-wheeling-diode) (see note 3) 2 PS with the same clamping voltage, but different nominal current (see note 4)
Imax,OUTx Max Imax,OUTy 0.75 x (Imax,OUTx + Imax,OUTy) Min
Ron,OUTx x Ron,OUTy Ron,OUTx + Ron,OUTy
Ron,OUTx x Ron,OUTy Ron,Ax + Ron,OUTy
ECl,OUTx ECl,OUTy
Ron,OUTx x Ron,OUTy Ron,OUTx + Ron,OUTy
2 PS with different nominal current and different clampMax ing voltage (see note 5)
Imax,OUTx Imax,OUTy
Clamping energy of the PS with the lower clamping voltage
Ron,OUTx x Ron,OUTy Ron,OUTx + Ron,OUTy
Final Data Sheet
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TLE 6244X
note 1: For every PS there exists only one symmetrical PS OUT1 and OUT2 are symmetrical PS. OUT3 and OUT4 are symmetrical PS. ... OUT17 and OUT18 are symmetrical PS. note 2: PS of the same type have the same nominal current and the same clamping voltage note 3: Parallel connection of PS-type 2,2A/45V with type 2,2A/70V note 4: Parallel connection of PS-type 2,2A/45V with type 3.0A/45V or Parallel connection of PS-type 1.1A/45V with type 2,2A/45V note 5: Parallel connection of PS-type 2,2A/70V with type 1.1A/45V or Parallel connection of PS-type 2,2A/70V with type 3.0A/45V
If the power stages are configured for static current limitation the max. current limitation of the parallel connected PS is the summation of the corresponding max. values of the PS (ISC,OUTx + ISC,OUTy +....). The following statements apply to Power Stages within different TLE6244X The application has to take into account that all maximum ratings of each TLE6244X are observed.
Final Data Sheet
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TLE 6244X
2. Maximum Ratings
2.1 Definition of Test Conditions The integrated circuit must not be destroyed if maximum ratings are reached. Every maximum rating is allowed to reach, as far as no other maximum rating is exceeded. Unless otherwise indicated all voltages are referred to GND (GND pins 1...8 connected to each other) Positive current flows into the pin. 2.2 Test Coverage (TC) in Series Production In the standard production flow not all parameters can be covered due to technical or economic reasons. Therefore the following test coverage was defined: A) Parameter test B) Go/NoGo test (in the course of release qualification/characterization: parameter test) C) Guaranteed by design (covered by lab tests, not considered within the standard production flow) 2.3 Thermal Limits Operating temperature TLE6244 continuous additionally only for the power switches (for 100h accumulated) Storage temperature Thermal resistance 2.4 Electrical Limits Limits must absolutely not be exceeded. By exceeding only one limit the integrated circuit might be destroyed. Power Supplies UVDD and UUBatt Static (without destruction) *) Dynamic <10sec (without destruction) -0.3V UVDD 36V -0.3V UUBatt 37V -0.5V UVDD 36V -0.5V UUBatt 40V -40C TJ 150C 150C TJ 200C -55C TC 125C RthJC 2,5 K/W
Dynamic (500 ms, 10 x in lifetime, without destruction) -0.5V UUBatt 40V *) UVDD > 5.5V is allowed only in case of error conditions! Not suitable for continuous operation. SPI Output Output voltage -0.3V USO 36V
Final Data Sheet
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TLE 6244X
Output current Outputs Low Side Switches Static voltage (without destruction) OUT1...6 OUT7..18
ISO 5mA
64V 40V
Dynamic voltage without destruction after ISO/DIS7637-1, pulses 1 to 4 OUT1 to 6, OUT9 to16: via external load (e.g. 2W lamp) 2ms OUT7, OUT8, OUT17 and OUT18: via external load 2ms Ground Current Total current GND1+2 (pins 26/27) (total ground current of OUT5,6,9,10,17,18) Total current GND3+4 (pins 58/59) (total ground current of OUT1,2,7,8,11,12,15,16) Total current GND5+6 (pins 11/12) (total ground current of OUT3,13) Total current GND7+8 (pins 41/42) (total ground current of OUT4,14) IGND1+2 18 A IGND3+4 20 A IGND5+6 6 A IGND7+8 6 A
Attention: Even if all ground pins are connected with each other on the PCB the total ground currents IGND1+2 and IGND3+4 and IGND5+6 and IGND7+8 must not be exceeded. The 4 ground pins GND1...4 are internally connected to the heat sink via an unspecified rivet joint. Therefore it is advisable to short-circuit the 4 ground pins on the PCB and to connect them with the heat sink. In addition the 4 ground pins GND5..8 must be connected to the other ground pins on the PCB Inputs of the Power Switches, SPI Inputs, Reset and Shut-off of the Power Stages Input voltage Input currents Pin RST Minimum reset duration (Power-On) Input currents 15 ms see 3.4.4 -0.3V UINi,RST,SS,SI,SCK,ABE 36V see 3.4.4 , 3.9.1 , 3.9.2 , 3.9.3 , 3.13.2
Final Data Sheet
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TLE 6244X
3. Electrical Characteristics
3.1 Operating Range (see also 3.13 VDD-monitoring ABE) Out of this range the power stages can be shut off by the VDD-monitoring except OUT8 Voltage referred to GND_ABE Minimum reset duration (Power-On) Minimum reset duration in operation mode 4.5V UVDD 5.5V 3.2 Validity of Parameters Parameters are valid for 4.5V UVDD 5.5V, 4.5V UUBatt 37V TLE6244: -40C TJ 150C and 2 power stages in current limitation unless otherwise noted. If VDD-monitoring is active the power stages are switched off except OUT8 (see page 28). Positive current flows into the pin, negative current flows out of the pin. Unless otherwise noted all voltages are referred to GND (GND1...8 connected with each other). If the UVDD falls below this trashed the power stages (except OUT8) are switched off. If UVDD rises above this threshold the power stages work regularly after a delay time of 250 sec. Threshold for shut off of OUT8: If UVDD rises above this threshold the power stages work regularly after a delay time of 250 sec. Supply voltage UVDD 3.5 4.2 4.5 V UVDD tRST,min tRST,min 4.7 15 1 5.3 V ms s
UVDD
3.5
V
UVDD
4.5
5.5
V
Final Data Sheet
44
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TLE 6244X
3.3 Power Consumption
UVDD 5.5V 5,5 V < UVDD < 36 V (IC is not destroyed) UUBatt = 14V UUBatt = 28V UUBatt UVDD Power consumption in standby mode in case of missing UVDD, UUBatt 14V
A C A A A A
IVDD IVDD IUBatt IUBatt IUBatt IUBatt
20 50 3 4 1 200
mA mA mA mA mA A
3.4 Inputs of the Power Stages and Reset IN1...IN16, RST 3.4.1 Low Level
Outputs are switched off if inputs are open (parallel control).
Reset not active, Power stage on for i = 1...5, 9...15 i = 6, 7, 16 Power stage off for i=8 Power stage off for i = 1...7, 9...16 Power stage on for i=8
B B B B B B B C
URSTL UINiL UINiL UINiL URSTH UINiH UINiH UINi, URST IINi,RST |IINi| IIN8 IIN8 IIN8 -IRST -IINi -100 20 20 20 5 40 40 40 10 1.7 2.0 2.0 0.1 -100
1.0 1.0 1.0 1.0
V V V V V V V V
3.4.2 High Level
3.4.3 Hysteresis 3.4.4 Input Currents In, RST -0.3V UINi,RST UVDD (i = 1...7, 9...16) UVDD UINi 36 V (i = 1...7, 9...16) -0.3V UIN8 UVDD 0.8V UIN8 UVDD, pull down UVDD UIN8 36 V, pull down 0V URST UVDD - 1.7V, pull up 0V UINi UVDD - 1.7V, pull up (i = 6,7,16) Bit BMUX = 1 (CONFIG_REG): 0V UINi UVDD - 1.7V, pull up (i = 1..5, 9..15) Bit BMUX = 0 (CONFIG_REG): 0V UINi UVDD, high-impedance (i = 1..5, 9..15)
0.6 5 5 100 100 100 100 20
V A A A A A A A
A/B C A/B A C A A
A
-IINi
20
40
100
A
A
|IINi|
1
A
Final Data Sheet
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TLE 6244X
3.4.5 Input Protection INi
Input clamping at INi (i = 1...16): No malfunction during clamping. Max. clamping current (externally limited) static dynamic (t < 2ms) Max. clamping voltage IINi = -5mA IINi = +2mA (t < 2ms) External current limitation at INi is only provided if sec-bus control is used. In that case INi are used as digital inputs. If sec-bus is not used, there is no external resistor for current limitation. See 2.4 "Inputs of the Power Switches, SPI Inputs..."
C C C C
|IINi| |IINi| UINi UINi -3 40
2 5
mA mA V V
70
3.5 Power Outputs 2.2A/70V OUT1...6
In case of open input (parallel control) or missing power supply the power stage is switched off. Parallel connection of power stages is possible. C IOUT1...6 > 2.2A Accumulated operating time C 100 h
IOUT1..6
3.5.1 Nominal Current 3.5.2 Extended Current Range
2.2
A
3.5.3 Maximum Current (Short Circuit Shut- down Threshold)
4.5V UUBatt 17V TJ = -40C TJ = 150C
B A
IOUT1..6 IOUT1..6
2.4 2.2
4.0 3.7
A A
UUBatt > 21V TJ = -40C TJ = 150C Above this limit short circuit to UBatt is detected. For the duration of the shutoff delay time tVoff (see 3.5.4) the output current is limited to approximately this value. If the short circuit condition is still present after tVoff, the output is switched off. An error is stored after tDiag (see 3.11.4).
B A
IOUT1..6 IOUT1..6
3 2.7
5.0 4.6
A A
Final Data Sheet
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TLE 6244X
Between -40C and 150C an approximately linear characteristic line can be assumed for the short circuit shutdown threshold. Between 17V UUBatt 21V, the short circuit shutdown threshold is switched. A power stage that is switched off in case of SCB can be switched on again by an off/on cycle at the corresponding input pin resp. by the change of the state of the corresponding SPI bit SCONx (see page 16), by the sec-Bus, by a DEL_DIA instruction or can be released again by reset. If the fault register is cleared before this release (by a DEL_DIA instruction), a new fault entry of SCB is immediately carried out, even if SCB condition is no longer present. 3.5.3.1 Maximum Battery Voltage at Short Circuit to Battery 3.5.4 Shutoff Delay 3.5.5 On Resistance See Note 1.11.1 C UOUT 1..6 36 V
Shutoff delay of the power stages after detection of SCB OUT1,2,5,6: TJ = 25C OUT1,2,5,6: TJ = 150C OUT1,2,5,6: TJ = -40C OUT3,4: TJ = 25C OUT3,4: TJ = 150C OUT3,4: TJ = -40C For UUBatt 10V Ron is increased up to 20%. On" Off" (Measurement with ohmic load) |tdon - tdoff| switch-on slew rate switch-off slew rate
B A A A A A A
tVoff
Ron1,2,5,6 Ron1,2,5,6 Ron1,2,5,6
60 220 420 180 210 410 170 320 600 250 300 580 240
215 400 750 310 380 720 300
s m m m m m m
Ron3, 4 Ron3, 4 Ron3, 4
3.5.6 On/off Delay Times
B B B C C C C
tdon1...6 tson1...6 tdoff1...6 tsoff1...6 td son1...6 soff1...6
10 5 10 10 5 15 21
s s s s s V/s V/s
Final Data Sheet
47
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TLE 6244X
3.5.7 Leakage Current
UVDD = 0V, UOUT1...6 = 14V (leakage current of the DMOS, diagnostic current = 0) UVDD = 0V, UOUT1...6 = 24V (leakage current of the DMOS, diagnostic current = 0)
A
IOUT1..6
50
A
A
IOUT1..6
200
A
3.5.8 Clamping 3.5.8.1 Clamping Voltage 3.5.8.2 Matching of the Clamping Voltage 3.5.8.3 Maximum Clamping Energy TC 110C IOUT1...6 = 0.2A Between different outputs with identical inductive loads Linear decreasing current, fmax = 50Hz (see diagrams E = f(I) on page 66) IOUT1...6 2.2A IOUT1...6 1.0A IOUT1...6 0.5A 3.5.8.4 Maximum Clamping Energy TC 60C Linear decreasing current, fmax = 50Hz C C C E E E 8.5 19 30 mJ mJ mJ A A
UOUT1..6
64
76 3
V V
U
IOUT1...6 2.2A IOUT1...6 1.0A IOUT1...6 0.5A 3.5.8.5 Maximum Clamping Energy with two Outputs connected in parallel 3.5.8.6 Maximum Clamping Energy at Load Dump 3.5.8.7 Jump Start Each output 75% of the values of 3.5.8.3 resp. 3.5.8.4
C C C C
E E E
10.8 22 36
mJ mJ mJ
For a maximum of 10 times during ECU life (load dump with 400ms and Ri = 2 over the load, e.g. 2W lamp) Each output 150% of the values of 3.5.8.4. For a maximum of 10 jump starts of 2 minutes each during ECU life. IOUT1...6 0.6A, max 10 000 pulse
C
E
50
mJ
C
3.5.8.8 Single pulse TC 60C
C
E
50
mJ
Final Data Sheet
48
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TLE 6244X
3.6 Power outputs 2.2A/45V OUT9...OUT14
In case of open input (parallel control) or missing power supply the power stage is switched off. Parallel connection of power stages is possible. C IOUTi > 2.2A Accumulated operating time C 100 h
IOUT9.. .14
3.6.1 Nominal Current 3.6.2 Extended Current Range 3.6.3 Maximum Current (Short Circuit Shut down Threshold)
2.2
A
4.5V UUBatt 17V for OUT11..14 4.5V UUBatt for OUT9/10 TJ = -40C TJ = 150C UUBatt > 21V for OUT11...14 TJ = -40C TJ = 150C For OUT11... OUT14 Above this limit short circuit to UBatt is detected. For the duration of the shutoff delay time tVoff (see 3.6.4) the output current is limited to approximately this value. If the short circuit condition is still present after tVoff, the outputs OUT11...OUT14 are switched off. An error is stored after tDiag (see 3.11.4). The same is true for OUT9, OUT10 if the static current limitation is not enabled. Between -40C and 150C an approximately linear characteristic line can be assumed. Between 17V UUBatt 21V, the short circuit shutdown threshold is switched for OUT11..14 B A B A IOUTi IOUTi IOUTi IOUTi 2.4 2.2 3 2.7 3.8 3.7 5 4.6 A A A A
Final Data Sheet
49
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TLE 6244X
A power stage that is switched off in case of SCB can be switched on again by an off/on cycle at the corresponding input pin resp. by the change of the state of the corresponding bit for SPI or sec-bus by a DEL_DIA instruction or can be released again by reset. If the fault register is cleared before this release (by a DEL_DIA instruction), a new fault entry of SCB is immediately carried out, even if SCB condition is no longer present. For OUT9, OUT10 Above this limit short circuit to UBatt is detected. The output current is limited to approximately this value if the static current limitation is configured. An error is stored after tDiag (see 3.11.4). If the operation leads to an overtemperature condition, a second protection level (about 170C) will change the output into a low duty cycle PWM (selective thermal shutdown with restart) to prevent critical chip temperatures Between -40C and 150C an approximately linear characteristic line can be assumed. 3.6.3.1 Maximum Battery Voltage at Short Circuit to Battery 3.6.4 Shutoff Delay See Note 1.11.1 C UOUT 9..14 36 V
Shutoff delay of the power stages after detection of KSUB. For the duration of tVoff current is limited to maximum current. TJ = 25C TJ = 150C TJ = -40C For UUBatt 10V Ron is increased up to 20%.
B
tVoff
60
215
s
3.6.5 On Resistance
A A A
Ron9-14 Ron9-14 Ron9-14
200 380 150
300 550 220
380 680 280
m m m
Final Data Sheet
50
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TLE 6244X
3.6.6 On /off Delay Times
On" Off" (Measurement with ohmic load) |tdon - tdoff| switch-on slew rate switch-off slew rate
B B B C C C C A
tdon tson tdoff tsoff td son soff IOUTi
10 5 10 10 5 20 25 50
s s s s s V/s V/s A
3.6.7 Leakage Current
UVDD = 0V, UOUT9...14 = 14V (leakage current of the DMOS, diagnostic current = 0) UVDD = 0V, UOUT9...14 = 24V (leakage current of the DMOS, diagnostic current = 0)
A
IOUTi
200
A
3.6.8 Clamping 3.6.8.1 Clamping Voltage 3.6.8.2 Maximum Clamping Energy TC 110C IOUTi = 0.2A Linear decreasing current, fmax = 30Hz (see diagrams E = f(I) on page 66) IOUT9...14 2.2A IOUT9...14 1.0A 3.6.8.3 Maximum Clamping Energy TC 60C Linear decreasing current, fmax = 30Hz C C E E 14 30 mJ mJ A U9...14 40 45 50 V
IOUT9...14 2.2A IOUT9...14 1.0A 3.6.8.4 Maximum Clamping Energy with two Outputs connected in parallel 3.6.8.5 Maximum Clamping Energy at Load Dump 3.6.8.6 Jump Start Each output 75% of the values of 3.6.8.2 resp. 3.6.8.3.
C C C
E E
17 36
mJ mJ
For a maximum of 10 times during ECU life (load dump with 400ms and Ri = 2 over the load, e.g. 2W lamp) Each output 150% of the values of 3.6.8.3. For a maximum of 10 jump starts of 2 minutes each during ECU life. IOUT9...14 0.6A, max 10 000 pulse
C
E
50
mJ
C
3.6.8.7 Single pulse TC 60C
C
E
50
mJ
Final Data Sheet
51
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TLE 6244X
3.7 Power outputs 3.0A/45V OUT15...OUT16
In case of open input (parallel control) or missing power supply the power stage is switched off. Parallel connection of power stages is possible. C IOUT15,16 > 3.0A Accumulated operating time C B A
IOUT15 IOUT16
3.7.1 Nominal Current 3.7.2 Extended Current Range 3.7.3 Maximum Current (Short Circuit Shut down threshold)
IOUT15 IOUT16
3.0
A
100 3.3 3 6 5.5
h A A
UUBatt > 4.5V TJ = -40C TJ = 150C Above this limit short circuit to UBatt is detected. For the duration of the shutoff delay time tVoff (see 3.6.4) the output current is limited to approximately this value. If the short circuit condition is still present after tVoff, the outputs OUT15/16 are switched off if the static current limitation is not enabled. An error is stored after tDiag (see 3.11.4). Above this limit short circuit to UBatt is detected. The output current is limited to approximately this value if the static current limitation is configured. An error is stored after tDiag (see 3.11.4). If the operation leads to an overtemperature condition, a second protection level (about 170C) will change the output into a low duty cycle PWM (selective thermal shutdown with restart) to prevent critical chip temperatures. Between -40C and 150C an approximately linear characteristic line can be assumed.
3.7.3.1 Maximum Battery Voltage at Short Circuit to Battery 3.7.4 Shuttoff Delay
See Note 1.11.1
C
UOUT 15,16
36
V
Shutoff delay of the power stages after detection of SCB. For the duration of tVoff current is limited to maximum current.
B
tVoff
60
215
s
Final Data Sheet
52
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TLE 6244X
3.7.5 On Resistance
TJ = 25C: TJ = 150C: TJ = -40C: For UUBatt 10V Ron is increased up to 20%.
A A A
Ron15,
16 16 16
150 270 120
220 390 170
280 480 210
m m m
Ron15, Ron15,
3.7.6 On /off Delay Times
On" Off" (Measurement with ohmic load) |tdon - tdoff| switch-on slew rate switch-off slew rate
B B B C C C C A
tdon tson tdoff tsoff td son soff IOUT15
,16
10 5 10 10 5 20 25 50
s s s s s V/s V/s A
3.7.7 Leakage Current
UVDD = 0V, UOUT15,16 = 14V (leakage current of the DMOS, diagnostic current = 0) UVDD = 0V, UOUT15,16 = 24V (leakage current of the DMOS, diagnostic current = 0)
A
IOUT15
,16
200
A
3.7.8 Clamping 3.7.8.1 Clamping Voltage 3.7.8.2 Maximum Clamping Energy TC 110C IOUT15,16 = 0.2A Linear decreasing current, fmax = 30Hz (see diagrams E = f(I) on page 67) IOUT15,16 3.0A IOUT15,16 2.2A IOUT15,16 1.5A IOUT15,16 1.0A 3.7.8.3 Maximum Clamping Energy TC 60C Linear decreasing current, fmax = 30Hz C C C C E E E E 18 20 24 40 mJ mJ mJ mJ UOUT15,
16
40
45
50
V
IOUT15,16 3.0A IOUT15,16 1.0A 3.7.8.4 Maximum Clamping Energy with two Outputs connected in parallel Each output 75% of the values of 3.7.8.2 resp. 3.7.8.3.
C C C
E E
20 46
mJ mJ
Final Data Sheet
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TLE 6244X
3.7.8.5 Maximum Clamping Energy at Load Dump 3.7.8.6 Jump Start
For a maximum of 10 times during ECU life (load dump with 400ms and Ri = 2 over the load, e.g. 2W lamp) Each output 150% of the values of 3.7.8.3. For a maximum of 10 jump starts of 2 minutes each during ECU life. IOUT15, 16 0.6A, max 10 000 pulses In case of open input (parallel control) or missing power supply the power stage is switched off. Parallel connection of power stages is possible. for OUT7, 8, 17, 18 IOUT7,8,17,18 > 1.1A Accumulated operating time
C
E
50
mJ
C
3.7.8.7 Single pulse TC 60C 3.8 Power Outputs 1.1A/45V OUT7,8, OUT17,18 3.8.1 Nominal Current 3.8.2 Extended Current Range 3.8.3 Maximum Current (Short Circuit Shut down Threshold and static current limitation)
C
E
50
mJ
C
IOUTi
1.1
A
C
100
h
4.5V UUBatt 17V for OUT7, 8 4.5V UUBatt for OUT17,18 TJ = -40C TJ = 150C B A IOUTi IOUTi 1.2 1.1 2.2 2.0 A A
UUBatt > 21V only for OUT7,8 TJ = -40C TJ = 150C For OUT7, OUT8 Above this limit short circuit to UBatt is detected. For the duration of the shutoff delay time tVoff (see 3.8.4) the output current is limited to approximately this value. If the short circuit condition is still present after tVoff, the outputs OUT7/8 are switched off. An error is stored after tDiag (see 3.11.4). The same is true for OUT17 OUT18 if the static current limitation is not enabled.
B A
IOUTi IOUTi
1.5 1.3
2.5 2.3
A A
Final Data Sheet
54
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TLE 6244X
Between -40C and 150C an approximately linear characteristic line can be assumed. Between 17V UUBatt 21V, the short circuit shutdown threshold is switched for OUT7/8 A power stage that is switched off in case of SCB can be switched on again by an off/on cycle at the corresponding input pin resp. by the change of the state of the corresponding bit for SPI or sec-bus by a DEL_DIA instruction or can be released again by reset. If the fault register is cleared before this release (by a DEL_DIA instruction), a new fault entry of SCB is immediately carried out, even if SCB condition is no longer present. For OUT17, OUT18 Above this limit short circuit to UBatt is detected. The output current is limited to approximately this value if the static current limitation is configured. An error is stored after tDiag (see 3.11.4). If the operation leads to an overtemperature condition, a second protection level (about 170C) will change the output into a low duty cycle PWM (selective thermal shutdown with restart) to prevent critical chip temperatures Between -40C and 150C an approximately linear characteristic line can be assumed. 3.8.3.1 Maximum Battery Voltage at Short Circuit to Battery 3.8.4 Shutoff Delay See Note 1.11.1 C UOUT 17,18 36 V
Shutoff delay of the power stages after detection of SCB. For the duration of tVoff current is limited to maximum current.
B
tVoff
60
215
s
Final Data Sheet
55
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TLE 6244X
3.8.5 On Resistance
TJ = 25C TJ = 150C TJ = -40C
For UUBatt 10V Ron is increased up to 20%; condition: UVDD > 4.5 V
A A A
Ron7,8, Ron7,8, Ron7,8,
17,18 17,18 17,18
400 780 290
620 1200 450
780 1500 560
m m m
For OUT8 only: 3.5V<(UVDD, UUBatt)<4.5V TJ = 25C TJ = 150C TJ = -40C 3.8.6 On/off Delay Times On" Off" (Measurement with ohmic load) |tdon - tdoff| Switch-on slew rate Switch-off slew rate 3.8.7 Leakage Current For OUT7,8, OUT1718: UVDD = 0V, UOUTi = 14V (leakage current of the DMOS, diagnostic current = 0) UVDD = 0V, UOUTi = 24V (leakage current of the DMOS, diagnostic current = 0) 3.8.8 Clamping 3.8.8.1 Clamping Voltage 3.8.8.2 Maximum Clamping Energy TC 110C For OUT7,8, OUT17,18: IOUTi = 0.2A Linear decreasing current, fmax = 10Hz (see diagrams E = f(I) on page 67) IOUTi 0.6A IOUTi 1.1A Linear decreasing current, fmax = 10Hz IOUTi 0.6 IOUTi 1.1A
A A A B B B C C C C
Ron Ron Ron tdon tson tdoff tsoff td son soff
1300 2200 1050 10 5 10 10 5 25 40
m m m s s s s s V/s V/s
A
IOUTi
50
A
A
IOUTi
200
A
A
UOUTi
40
45
50
V
C C
E E
10 7
mJ mJ
3.8.8.3 Maximum Clamping Energy TC 60C
C C
E E
12 8.5
mJ mJ
Final Data Sheet
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TLE 6244X
3.8.8.4 Maximum Clamping Energy with two Outputs connected in parallel 3.8.8.5 Maximum Clamping Energy at Load Dump 3.8.8.6 Jump Start
Each output 75% of the values of 3.8.8.2 resp. 3.8.8.3.
C
For a maximum of 10 times during ECU life (load dump with 400ms and Ri = 2 over the load) Each output 150% of the values of 3.8.8.3. For a maximum of 10 jump starts of 2 minutes each during ECU life
C
E
15
mJ
C
Final Data Sheet
57
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TLE 6244X
3.9 SPI Interface The timing of TLE6244X is defined as follows: - The change at output (SO) is forced by the rising edge of the SCK signal. - The input signal (SI) is sampled on the falling edge of the SCK signal. - The data received during a writing access is taken over into the internal registers on the rising edge of the SS signal, if exactly 16 SPI clocks have been counted during SS = active. (Also: Only if exactly 16 SPI clocks have been counted the instruction DEL_DIA resets the diagnostic registers.)
10
9
SS 2 SCK 1 11 3 8
13 4
14 12 7
SO
tristate
Bit (n-3)
Bit (n-4)...1
Bit 0; LSB
5
6
SI
MSB IN
Bit (n-2)
Bit (n-3)
Bit (n-4)...1
LSB IN X see 3.9.5
n = 16
Final Data Sheet
58
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TLE 6244X
3.9.1 Input SCK 3.9.1.1 Low Level 3.9.1.2 High Level 3.9.1.3 Hysteresis
3.9.1.4 Input Capacity
SPI clock input B B C C Pull up current source connected to VDD Slave select signal TLE6244X is selected B B C C Pull up current source connected to VDD SPI data input B B C C Pull up current source connected to VDD Tristate output of the TLE6244X (SPI output); On active reset (RST) output SO is in tristate. ISO = 2mA ISO = -2mA Capacity of the pin in tristate In tristate A A C A USOL USOH CSO ISO -10 UVDD - 1.0 10 10 0.4 V V pF A A USIL USIH USI CSI -ISI 10 20
2.0 1.0
USCKL USCKH
USCK
1.0 2.0
V V V pF A
0.1 10 20
0.6 10 50
CSCK -ISCK
3.9.1.5 Input Current
A
3.9.2 Input SS 3.9.2.1 Low Level 3.9.2.2 High Level 3.9.2.3 Hysteresis 3.9.2.4 Input Capacity 3.9.2.5 Input Current
USSL USSH USS CSS -ISS 10 20
2.0
1.0
V V V pF A
0.1
0.6 10 50
A
3.9.3 Input SI 3.9.3.1 Low Level 3.9.3.2 High Level 3.9.3.3 Hysteresis 3.9.3.4 Input Capacity 3.9.3.5 Input Current
V V V pF A
0.1
0.6 10 50
3.9.4 Output SO
3.9.4.1 Low Level 3.9.4.2 High Level 3.9.4.3 Capacity 3.9.4.4 Leakage Current
Final Data Sheet
59
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TLE 6244X
3.9.5 Timing
1. Cycle-Time (referred to master) 2. Enable Lead Time (referred to master) 3. Enable Lag Time (referred to master) 4. Data Valid CL = 50pF (5 MHz) Data Valid CL = 200pF (2MHz) (referred to TLE6244X) 5. Data Setup Time (referred to master) 6. Data Hold Time (referred to master) 7. Disable Time (referred to TLE6244X) 8. Transfer Delay (referred to master) 9. Select time (referred to master) 10. Access time (referred to master) 11. Serial clock high time (referred to master) 12. Serial clock low time 13. Disable Lead Time
B C C C C C C C C C C C C C
t cyc t lead t lag tv tv t su th t dis t dt t sel t acc tSCKH tSCKL tdld
200 100 150 100 150 50 20 100 150 50 8.35 50 120 250
ns ns ns ns ns ns ns ns ns nsec sec ns ns ns
C 14. Disable Lag Time tdlg 250 ns
Final Data Sheet
60
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TLE 6244X
3.10 sec-bus
tcyc
FCL/IN16
tsetup
FDA/IN6 SSY/IN7
thold tshold tSF
tswitch
Timing sec-bus
Notes for the timing:
Timing definitions are starting or ending at a voltage level of 1V (Low Level) resp. 2V (High Level).
During SSY = high the clock at FCL may be interrupted, i.e. there is no need for a clock during SSY = high. The clock signal may remain on high or low statically during SSY = high. A rising edge at SSY and a falling edge at FCL must not occur simultaneously! On the rising edge of SSY the 16 bits clocked in TLE6244X by the last 16 falling edges at FCL are latched. 3.10.1 Input FCL, FDA, SSY 3.10.1.1 Low Level sec-bus interface pins B UFCLl UFDAl USSYl UFCLh UFDAh USSYh
UFCL UFDA USSY
1.0
V
3.10.1.2 High Level
B
2.0
V
3.10.1.3 Hysteresis 3.10.1.4 Input Capacity 3.10.1.5 Input Current 3.10.2 Timing Pull up current source connected to VDD Cycle Time Data setup time Data hold time Switching time on FCL fFCL < 10MHz
C C
0.1
0.6 10
V pF
CFCL CFDA CSSY IFCL IFDA ISSY tCYC tsetup thold tswitch 5 10
A
20
A
C C C C
62 10 10 30
nsec nsec nsec nsec
Final Data Sheet
61
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TLE 6244X
Switching time on FCL fFCL > 10MHz Select hold time FCL Low time FCL High time SSY Low time SSY High time Time between rising edge of SSY and next falling edge of FCL 3.11 Diagnostics 3.11.1 Diagnostic Thresholds Power Stages 3.11.1.1 Open Load (OL) 3.11.1.2 Short to Ground (SCG) Output turned off
C C C C C C C
tswitch tshold
tFCLL tFCLH tSSYL tSSYH tSF
8 25 25 25 25 25 8 10
nsec nsec nsec nsec nsec
B
UOUT1..
18
UVDD 0.5V 0.54 * UVDD 0.5V
-
UVDD
UVDD 0.5V
+
V
Output turned off
B
UOUT1...
18
0.54 * UVDD
0.54 * UVDD 0.5V
+
V
3.11.1.3 Short to Battery (SCB) 3.11.1.4 Overtemperature 3.11.2 Bias Voltage Open Load Power Stages 3.11.3 Diagnostic Currents Power Stages
See 3.5.3, 3.6.3, 3.7.3, 3.8.3 Output turned on Individually for each stage Output turned off, IOUT1...18 = 0 B A TJ UOUT1...
18
150 0.6 * UVDD 0.7 * UVDD 0.76* UVDD
C V
4.5V UVDD 5.5V, output turned off UOUT1...18 = 14V (diagnostic current incl. leakage current) UOUT1...18 = 0V UOUT1...18 = OL-Threshold UOUT1...18 = SCG-Threshold A A C C IOUT -IOUT IOUT -IOUT 270 50 220 40 580 130 980 250 980 250 A A A A
Final Data Sheet
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TLE 6244X
3.11.4 Filtering Time Power Switches
Time from occurrence of one of the errors 'short to ground', 'open load' or 'short to battery' until the fault is entered into the corresponding diagnostic register. Time from occurrence of OT until the information is entered into the corresponding diagnostic register.
B
tDiag
60
240
s
C
tDiatOT
3
30
s
3.11.5 Diagnostic Threshold UBatt 3.12 Reverse Currents 3.12.1 Reverse Current at OUT1...18 without Supply Voltage
Bit Ubatt in DIA_REG5
Uth,UB
1
9
V
UVDD 1V Static C C C C C C C C -IO1...6 -IO9...16 -IO7,8 -IO17,18 -IO1...6 -IO9...16 -IO7,8 -IO17,18 3 3 0.8 0.8 10 10 1.5 1.5 A A A A A A A A
Dynamic (Test pulse 1 according to ISO: 100V, Ri = 10W, 2ms) 3.12.2 Reverse Current at OUT1...OUT18 in Operation Mode 4.5V UVDD 5.5V Pulsed power stage. Neighboring stages, reset, input signals of the power stages, VDDmonitoring, SPI interface (incl. registers) and sec-bus must not be disturbed. Diagnostics of fault conditions at neighboring stages is still possible. Control bits in the SPI registers (serial control of power stages are not disturbed). Open load failure at neighboring stages may be detected as short to ground Open load failure at neighboring stages are not detected as short to ground Destruction limit
C C C C C C C C C C C
-IO1...16 -IO7,8 -IO17,18 -IO1...4 -IO5...16 -IO7,8 -IO17,18 -IO1...6 -IO9...16 -IO7,8 -IO17,18
1 0.3 0.3 0.5 0.25 0.3 0.3 3 3 0.8 0.8
A A A A A A A A A A A
Final Data Sheet
63
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TLE 6244X
3.13 VDD-Monitoring ABE
Bidirectional: open drain output / input with pull up current source An external current limitation must guarantee IABE < 5 mA for any UABE UABE = Low (after tglitch)for: 2.7V < UVDD < 4.5V... 4.7V or 5.3V... 5.5V < UVDD < 36V or Testmode (see 3.13.5 or 3.13.6) or Pin GND_ABE is open UVDD > 4.5V, IABE<5mA UVDD = 2.7V, IABE<1mA, in case of less current, ohmic behavior can be assumed A A UABE UABE 1.2 1.0 V V
3.13.1 Output
3.13.1.1 Low Level
3.13.1.2 Maximum Voltage
No current recovery on VDD, UBatt and the logical pins (SS,SCK,SI,SO,INx,RST) in case of short to battery at ABE (up to 36V)
C
UABE
36
V
3.13.2 Input 3.13.2.1 Low Level 3.13.2.2 High Level 3.13.2.3 Hysteresis 3.13.2.4 Input Current Pull up current source connected to VDD -0.25V UABE UVDD-1.7 V -0.25V UABE UVDD-1.5 V -0.3V UABE < -0,25V 3.13.3 Overvoltage Threshold Voltage referred to GND_ABE A C C B -IABE -IABE -IABE VDDth_h 20 15 5.3 40 40 100 100 300 5.5 A A A V B B C UABEL UABEH UABE
0.7 * UVDD 0.3 * UVDD
V V
0.2
1.0
V
Final Data Sheet
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TLE 6244X
3.13.4 Undervoltage Threshold 3.13.5 Test Mode: Reducing the Overvoltage Threshold 3.13.6 Test Mode: Lifting the Undervoltage Threshold 3.13.7 Suppression of Glitches
Voltage referred to GND_ABE
B
VDDth_l
4.5
4.7
V
Voltage referred to GND_ABE
B
VDDth_h
4.5
4.7
V
Voltage referred to GND_ABE
B
VDDth_l
5.3
5.5
V
Periodical alternating between overvoltage and normal operating voltage with T< 50s and overvoltage duration > 5s leads to overvoltage detection. If the transition from undervoltage to overvoltage is faster than the filtering time tglitch, the filtering time tglitch for overvoltage detection is not started again. The same is valid for reverse order.
A
tglitch
50
215
s
3.13.8 GND_ABE 3.13.8.1 Permissible Offset between GND_ABE and GND 3.13.8.2 Bond Lift / Solder Crack on GND_ABE Pin ABE goes LOW (see 3.13.1.1). The power stages are switched off. The over- and undervoltage thresholds are increased by typically 700mV for TA = 25C. C UGND 0.3 V
Final Data Sheet
65
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TLE 6244X
3.14 Clamping Energy 3.14.1 E = f(IOUT1...6), 2.2A Power Stages with 70V Clamping E / mJ
30
+ +
Injector Drivers Clamping Voltage 64... 76V fmax = 50 Hz TCmax = 110C
20
+
10
+ + +
0 0 0.5 1.0 1.5 2.0 IMAX / A
3.14.2 E = f (IOUT9...A14), 2.2A Power Stages with 45V Clamping E / mJ
30
+ +
2.2A Power Stage Clamping Voltage 40... 50V fmax = 30 Hz TCmax = 110C
20
+ + +
10
0 0 0.5 1.0 1.5 2.0 IMAX / A
Final Data Sheet
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TLE 6244X
3.14.3 E = f(IOUT7,8,17,18), 1100mA Power Stages with 45V Clamping E / mJ
15
1.1A Power Stage Clamping Voltage 40... 50V fmax = 10 Hz TCmax = 110C
+
10
+
5
+
0 0 0.25 0.5 0.75 1.0 IMAX / A
3.14.4 E = f(IOUT15, OUT16), 3.0A Power Stages with 45V Clamping E / mJ
30
+ +
3.0A Power Stage Clamping Voltage 40... 50V fmax = 30 Hz TCmax = 110C
20 + + 10
0 0 0.5 1.0 1.5 2.0 2.5 IMAX / A
Final Data Sheet
67
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TLE 6244X
4. ESD
All pins of the IC have to be protected against electrostatic discharge (ESD) by appropriate protection components. The integrated circuit has to meet the requirements of the Human Body Model" with UC = 2kV, C = 100pF and R2 = 1,5k without any defect or destruction of the IC. Appropriate measures to reach the required ESD capability have to be coordinated. The ESD capability of the IC has to be verified by the following test circuit.
S2
(1) R1 US S1
(2) R2
V
DC-Voltmeter
C
UC
DUT
S3
UC = + 2kV R1 = 100k R2 = 1,5k C = 100pF Number of pulses each pin: 18 in all Frequency: 1Hz Arrangement and performance: The requirements of MIL883D Method 3015 (latest revision) have to be fulfilled.
Final Data Sheet
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TLE 6244X
5. Package Outline
Final Data Sheet
69
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TLE 6244X
Edition 2003-08-29 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 11/28/03. All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Final Data Sheet
70
V4.2, 2003-08-29

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